1. Field of Invention
Embodiments of the present invention relate generally to electronic devices and, more specifically, in certain embodiments, to memory devices.
2. Description of Related Art
Generally, memory devices include an arrangement of addressable memory cells. For example, some devices include a number of floating-gate transistors positioned according to a grid of conductors. One set of conductors, referred to as “data lines,” connects to the floating-gate transistors via their sources or drains, and another set of conductors, referred to as “control lines,” connects to control gates of the floating-gate transistors. The control lines and the data lines are often generally perpendicular to each other, and typically, a floating-gate transistor lies near each intersection of a data line and a control line. As a result, each floating-gate transistor may be accessed, e.g., read, erased, or programmed, through a unique control-line, data-line pair.
In some systems, accessing a memory cell can corrupt data stored by other memory cells. Typically, each data line and each control line connect to a plurality of memory cells, so a stimulus (e.g., voltage or current) asserted through a selected data line or a selected control line could affect memory cells other than the one being accessed. For example, certain floating-gate transistors are programmed by asserting a program voltage through a selected control line. The voltage programs the memory cell being accessed, but it could also affect the data stored by other memory cells connected to the same control line. This effect is referred to as “program disturb.”
Program disturb is mitigated, in part, by certain conventional techniques, such as asserting a pattern of pass voltages on unselected control lines while floating the unselected data lines. During programming, the unselected control lines capacitively couple to the unselected data lines, and this capacitive coupling counteracts the effect of the program voltage on the unselected memory cells connected to the selected controlline. Electric fields from the pass voltages drive charges toward the memory cells that are at highest risk of program disturb, i.e., the memory cells that are on the selected control line and the unselected data lines. These charges counteract the effect of the program voltage on unselected memory cells by elevating the voltage under the unselected memory cells and lowering the voltage drop across the unselected memory cells. The selected memory cell is not as affected by the pass voltage because the selected data line is not isolated. This technique is referred to as “self-boosting.”
Some conventional self-boosting techniques introduce other problems. The pass-voltage patterns often include different voltages asserted on adjacent control lines or other conductors, and the differences in voltage can establish relatively large electric fields between the adjacent structures. These fields are believed to inject stray charges, such as hot electrons or hot holes, into some memory cells, thereby corrupting stored data.